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Altera Corporation 21
MAX 9000 Programmable Logic Device Family Data Sheet
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 9000 Device
The time required to program a single MAX 9000 device in-system can be
calculated from the following formula:
where: t
PROG
= Programming time
t
PPULSE
= Sum of the fixed times to erase, program, and
verify the EEPROM cells
Cycle
PTCK
=Number of TCK cycles to program a device
f
TCK
= TCK frequency
The ISP times for a stand-alone verification of a single MAX 9000 device
can be calculated from the following formula:
where: t
VER
=Verify time
t
VPULSE
= Sum of the fixed times to verify the EEPROM cells
Cycle
VTCK
=Number of TCK cycles to verify a device
t
PROG
t
PPULSE
Cycle
PTC
K
f
TCK
-----------------------------
---
+=
t
VER
t
VPULSE
Cycle
VTC
K
f
TCK
-----------------------------
---
+=
- MAX 9000 1
- ...and More 2
- Features 2
- General 3
- Description 3
- 4 Altera Corporation 4
- Functional 5
- Logic Array Blocks 6
- Macrocells 8
- Altera Corporation 9 9
- Expander Product Terms 10
- Parallel Expanders 11
- FastTrack Interconnect 12
- Macrocell 1 14
- Macrocell 2 14
- Local Array 14
- Row-to-I/O Cell Connections 15
- I/O Cells 16
- Dedicated Inputs 16
- Configuration 18
- In-System 19
- Programma 19
- Programming Sequence 20
- Programming Times 20
- Programmable 26
- Speed/Power 26
- Design Security 26
- Generic Testing 26
- Operating 27
- Conditions 27
- Timing Model 30
- Macrocell 31
- -10 -15 -20 32
- Min Max Min Max Min Max 32
- Table 23. IOC Delays 34
- MinMaxMinMaxMinMax 34
- Consumption 35
- Figure 15. I 37
- Pin-Outs 38
- VPP pin is pulled up 41
- Revision 44
- Altera Corporation 45 45
- 46 Altera Corporation 46
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