Z Microsystems ZX3 Manual de usuario descargar pdf (Pagina 22)

22 Altera Corporation

MAX 9000 Programmable Logic Device Family Data Sheet

The programming times described in Tables 7 through 9 are associated

with the worst-case method using the ISP algorithm.

Tables8 and 9 show the in-system programming and stand alone

verification times for several common test clock frequencies.

Table 7. MAX 9000 t

PULSE

& Cycle

TCK

Values

Device Programming Stand-Alone Verification

PPULSE

(s) Cycle

PTCK

VPULSE

(s) Cycle

VTCK

EPM9320

EPM9320A

11.79 2,966,000 0.15 1,806,000

EPM9400 12.00 3,365,000 0.15 2,090,000

EPM9480 12.21 3,764,000 0.15 2,374,000

EPM9560

EPM9560A

12.42 4,164,000 0.15 2,658,000

Table 8. MAX 9000 In-System Programming Times for Different Test Clock Frequencies

Device f

TCK

Units

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

EPM9320

EPM9320A

12.09 12.38 13.27 14.76 17.72 26.62 41.45 71.11 s

EPM9400 12.34 12.67 13.68 15.37 18.73 28.83 45.65 79.30 s

EPM9480 12.59 12.96 14.09 15.98 19.74 31.03 49.85 87.49 s

EPM9560

EPM9560A

12.84 13.26 14.50 16.59 20.75 33.24 54.06 95.70 s

Table 9. MAX 9000 Stand-Alone Verification Times for Different Test Clock Frequencies

Device f

TCK

Units

10 MHz 5 MHz 2 MHz 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz

EPM9320

EPM9320A

0.33 0.52 1.06 1.96 3.77 9.18 18.21 36.27 s

EPM9400 0.36 0.57 1.20 2.24 4.33 10.60 21.05 41.95 s

EPM9480 0.39 0.63 1.34 2.53 4.90 12.02 23.89 47.63 s

EPM9560

EPM9560A

0.42 0.69 1.48 2.81 5.47 13.44 26.73 53.31 s

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 45 46

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